In order to satisfy the quality of HDTV (high-definition television) level, the performance of 10 Mbps or more is required in an image contraction and expansion device. To realize this, it is necessary to decode data coded on the basis of the variable-length codes, for each clock. For doing this, it is necessary to automatically select heads of the continuous variable-length codes for each clock. The heads thereof can be selected by barrel shift on the basis of the code lengths of the variable-length codes.
FIG. 5 shows a conventional VLD (variable-length decoder). In the drawing, data are applied in unit of 32 bits from an FIFO (first-in first-out) memory 1 to a shift circuit 3 for VLD via an interface section 2. To the shift circuit 3, decode length information DLT is given from a look-up table via an accumulative adder 5. Therefore, the shift circuit 3 barrel-shifts (32 bit.times.2) data to select the heads in sequence and repeatedly. The interface section 2, the shift circuit 3 and the accumulative adder 5 constitute a head shifter section.
The operation of the VLD shown in FIG. 5 will be explained simply hereinbelow. Data of the external FIFO memory 1 are given to the interface section 2 in unit of 32 bits on the basis of a signal Read given by the accumulative adder 5. In the interface section 2, 32-bit data D0, D1, D2, . . . are stored in sequence in three registers R20, R21 and R22 on the basis of a signal Carry applied by the accumulative adder 5, and then updated in sequence in first-in and first-out manner. Further, data are inputted from the registers R20 and R21 to a first barrel shifter BS0 of the shift circuit 3. The first barrel shifter BS0 shifts 64-bit data from the registers R20 and R21 within a range from 0 to 31 bits on the basis of a shift length signal SH0 (the accumulatively added code length of the variable-length codes) of the accumulative adder 5, and then outputs the shifted data as 32-bit data. In other words, the first barrel shifter BS0 shifts the inputted data on the basis of a decode signal obtained by decoding the shift length signal SH0 through a decoder DC0. The shifted data are transmitted to a second barrel shifter BS1 via a register R31 as less significant bit side data. In the second barrel shifter BS1, the 32-bit more significant side data of the second barrel shifter BS1 are latched by a latch R30 and then applied to the same second barrel shifter BS1 as the preceding cycle data. The second barrel shifter BS1 shifts the inputted 64-bit data within the range from 0 to 31 bits on the basis of a shift length signal SH1 (a code length of the variable-length code decoded in the preceding cycle) applied by the accumulative adder 5, and outputs the shifted data as 32-bit data. In other words, the second barrel shifter BS1 shifts the inputted data on the basis of a decode signal obtained by decoding the shift length signal SH1 by a decoder DC1. The data of the second barrel shifter BS1 are given to the look-up table 4, form which the decode length information DLT is given to the second barrel shifter BS1 and the accumulative adder 5 via a register R50 as the signal SH1. An adder add of the accumulative adder 5 adds the contents of both the registers R50 and R51. The output of the adder add is given to the first barrel shifter BS0 as the signal SH0. When the output of the adder add exceeds "31", s signal carry is outputted. The outputted signal carry is given to the interface section 2 and further to the FIFO memory 1 as the signal Read via a resister R52, as already explained.
FIG. 6 shows a more practical circuit of the shift circuit 3, in which each data block is shown in unit of 4 bits for brevity (in FIG. 5, each data block is shown in unit of 32 bits). As understood in FIG. 6, the barrel shifter BS0 and BS1 are of the same configuration from the standpoint of hardware. That is, in the first barrel shifter BS0, a wiring area LA for data input lines dI(01) to dI(07) is positioned on the left side in FIG. 6, and an element area EA is positioned on the right side. In more detail, 16 element units (transistors) are arranged roughly into a matrix pattern in the element area EA. One end of each of these element units U arranged obliquely is connected to a data input line dI(0i) also arranged obliquely in correspondence to the obliquely-arranged element units in FIG. 6, and the other end of each of these element units U arranged in the column direction is connected to a bit line BL (i.e., a data output dout0(i)) arranged in the column direction in correspondence to the column-arranged element units. The gate of each of these element units U arranged in the row direction is connected to a select line SL(0i) arranged in the row direction in correspondence to the row-arranged element units U. Further, the other barrel shifter BS1 is constructed roughly in the same way as above. Therefore, when data are shifted 2 bits by the first barrel shifter BS0 on the basis of the shift signal SH0, the select line SL(02) is activated to turn on the element units U whose gates are connected thereto, so that the input data din00 can be shifted by 2 bits.
In the conventional device, as described above with reference to FIG. 5, registers R30 and R31 are interposed as pipe-line registers between the first and second barrel registers BS0 and BS1. In other words, since two registers are needed, the area occupied by the these registers increases. In addition, since the output dout0 of the first barrel register BS0 is applied to the second barrel register BS1 via the register R31, when 1-bit data is taken into account, it is impossible to use a single data line extending from the input of the first barrel register BS0 to the output of the second barrel register BS1. Therefore, it is practically impossible to adopt such a method that a single sense amplifier is connected to the output side of a single data line to reduce the width of the data lines.
In addition, as understood by FIG. 6, when each barrel shifter is seen, only wires (input data lines dI) are arranged coarsely on the left side wiring area LA under such conditions that there are many gaps and dead spaces (on which no wires are arranged). In summary, the area availability is low in the device.